This invention relates to a method of and an apparatus for checking the geometry of multi-layer patterns for semiconductor structures such as for example LSI wafers.
Integrated circuits such as LSIs have a tendency to high integration and size reduction. It is frequent that defects occur in fine patterns of the integrated circuits during production of these patterns in spite of the fact that the patterns are carefully handled. Therefore, these patterns must be checked in detail.
Further, in a conventional checking process, many inspectors participate in checking the presence or absence of a small defect with the eye by using a microscope. But through repeated inspections, the inspector becomes tired with eyes to overlock defects, and reliability is restricted from the standpoint of quality control. The manual inspection, on the other hand, disturbs flow of production and becomes a cause for degrading productivity. Thus, with a view of improving quality insurance and productivity, it is a very important task to automate checking processes.
Patterns on a semiconductor device which can be an object to be checked in accordance with the present invention has a complicated three-dimensional structure as exemplified in FIG. 1. In checking such a three-dimensional structure, a conventional checking apparatus often fails to fulfill itself satisfactorily. For example, in a conventional apparatus as shown in FIG. 2, linear image sensors 5a and 5b have each a self-scanning function in the longitudinal direction and detect a one-dimensional pattern. An LSI wafer 1 is moved by an XY table 7 in a direction orthogonal to the linear image sensor scanning so that a two-dimensional patterns on a chip 2 can be detected. Objectives 4a and 4b focus illumination light beams 3a and 3b on the chip and defects enlarged chip patterns, and electric signals from the image sensors 5a and 5b are converted into digital signals by means of A/D converters 11a and 11b. The digital signals are converted by threshold circuits 12a and 12b into binary signals which in turn are fed to a collating circuit 13.
With the conventional apparatus for checking the geometry of wafer configured as above, the collating circuit 13 treats the binary signals and hence, the checking is grounded on an essential premise that two circuit patterns to be detected by the image sensors 5a and 5b are identical to each other.
In other words, it is a requisite that no misregistration exist between two detected image signals and only when this requisite is satisfied, the conventional binary comparison becomes valid.
Since, dependent on such factors as accuracies of an XY table carrying an object to be checked, accuracies of chip arrangement and thermal deformation of optical and mechanical system, misregistration inevitably occurs between input patterns it has been practice that the misregistration between the input patterns is measured and corrected to perform defect judgement. However, because of the threedimensional structure of patterns, an object to be checked may involve misregistration even between first and second layers thereof, that is, an inter-layer alignment error, with the result that a defect which is identical in size to or smaller than the inter-layer alignment error, even though being fatal, can not be discriminated from the interlayer alignment error. The inter-layer alignment error is a kind of misregistration which is inevitably caused when forming the patterns. However, according to the conventional method of detecting unmatching, a fine defect is covered with the inter-layer misregistration and is impossible to detect.
A conventional apparatus has been available, having a shift register for correcting misregistration, which shift register is however for compensating for errors in conversion of images into binary signals and can not meet improvements in accuracies of checking finely formed objects.
Specifically, when as shown in FIGS. 3A and 3B misregistration (alignment error) exists between a first layer pattern and a second layer pattern of a multi-layer pattern f.sub.1 on an object to be checked, for example, a semiconductor device in relation to another multi-layer pattern g.sub.2 on another object, a defect which is approximately identical in size to or smaller than the inter-layer alignment error can not be detected. When forming the multi-layer patterns, the misregistration standing for the inter-layer alignment error is inevitable. Thus, the unmatching detection following the registration according to the conventional techniques provides a result as shown in FIG. 3C, indicating that the detection of the defect alone is impossible.
In addition, the pattern is sometimes accompanied by fine unevenness or variations in width which constitute defects that can not be detected with only the conventional misregistration correcting means. Detection of such defects is also desired.
Known examples of inventions concerning registration are dssclosed in Japanese Patent Unexamined Publication Nos. 57-34402 and 57-196377.
Japanese Patent Unexamined Publication No. 58-46636 describes registration of a mask which is of a one-layer pattern. The mask not being of a multi-layer pattern never faces a problem of the inter-layer alignment error, and therefore a measure disclosed in the aforementioned publication will not be applied to a wafer which is an object to be checked in the present invention.